|
|
 |
| Patent |
Issued
|
Title |
|
5,204,836
|
1993
|
Method and Apparatus for Implementing Redundancy
in Parallel Memory Structures |
|
5,065,055
|
1991
|
Method and Apparatus for High-Speed BI-CMOS
Differential Amplifier with Controlled Output Voltage |
|
4,679,171
|
1987
|
MOS/CMOS Memory Cell |
|
4,667,311
|
1987
|
Dynamic RAM with Reduced Substrate Noise and
Equal Access and Cycle Time |
|
4,233,675
|
1980
|
X Sense Amp Memory |
|
4,069,474
|
1978
|
MOS Dynamic Random Access Memory Having an
Improved Sensing Circuit |
|
4,042,915
|
1977
|
MOS Dynamic Random Access Memory Having an
Improved Address Decoder Circuit |
|
4,031,522
|
1977
|
Ultra High Sensitivity Sense Amplifier for
Memories Employing Single Transistor Cells |
|
4,025,907
|
1977
|
Interlaced Memory Matrix Array Having Single
Transistor Cells |
|
3,937,983
|
1976
|
MOS Buffer Circuit |
|
3,876,887
|
1975
|
MOS Amplifier |
|
3,863,230
|
1975
|
MOS Memory Decoder Circuit |
|
3,858,185
|
1974
|
MOS Dynamic Memory Array and Refreshing System |
|
3,550,097
|
1970
|
DC Memory Array |
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